Makefile
(or makefile
)
that identifies compilation steps, outputs, and dependencies.
target: dependency1 dependency2 dependency3 all on one line command-to-produce-target-using-dependencies on next line
pp0b: myProj.h file1.c file2.c gcc -o pp0b file1.c file2.c
pp0b: myProj.h \ continue on next line file1.c \ continue on next line file2.c last dependency gcc -o pp0b file1.c file2.c command is on separate line
make
:
makeIf a target does not exist or any dependencies have been updated (newer than target),
make
will run the
command. It will not run commands for any targets
that are already up-to-date.
Makefile
(or makefile
):
make -f myMakefile
make -f myMakefile pp0b
This example has four targets: two executables (testpp1a
and disassembler
), a target that represents both
(all
), and a target that removes intermediate and final
output files (clean
).
all: testpp1a \ disassembler testpp1a: pp1.h \ printFuncs.h \ verifyMIPSInstruction.c \ binToDec.c \ printDebug.c \ printError.c \ testpp1a.c gcc verifyMIPSInstruction.c binToDec.c printDebug.c \ printError.c testpp1a.c -o testpp1a # The assembler will probably have other source files in addition to these. disassembler: disassembler.h \ printFuncs.h \ verifyMIPSInstruction.c \ binToDec.c \ getRegName.c \ printDebug.c \ printError.c \ disassembler.c gcc verifyMIPSInstruction.c binToDec.c getRegName.c \ printDebug.c printError.c disassembler.c -o disassembler clean: rm -rf *.o testpp1a disassembler